This invention relates to semiconductor memory devices, and more specifically to such memory devices having internal circuit means to generate raised power supply (hereinafter called internal supply line), and to the method of driving the memory devices.
Semiconductor memory devices in the current state of the arts contain an intermediary of power supplies, capable of outputting discrete levels of voltage, up or down of a rated voltage of an internal supply line, to energize constituent elements, as required, instead of directly applying an external line rated at VCC, so that the power dissipation and reliability of memory devices may be improved.
FIG. 1 shows a unit cell of DRAM (dynamic random access memory) including a switching transistor 11 and a memory capacitor 10. An n-channel MOS transistor is used in the DRAM cell, the drain D and the gate G being connected to a bit line 12 and a word line 13, respectively, and the source S to ground across the capacitor. If the internal supply line is charged at rated voltage, Vint, the transistor 11 will not switch on to conduct current between source S and drain D, unless the gate G is made more positive than the source S, by about equal to that of threshold voltage VT of the transistor 11.
At the onset of the address signals reception, a memory unit is selected and a transistor 11 is connected to bit line 12 and word line 13, accordingly. When a word line 13 is triggered with a high level signal, the transistor 11 switches on to cause a capacitor 10 to discharge and read memory current flows to the bit line 12, whereupon a sensing amplifier (not shown) initiates rewriting the capacitor with an electric charge equal to the storage memory data. With the industry arts progressing to larger integration, a smaller size will be demanded for memory capacitors, and will result in longer DRAM bit lines, with a consequence of a larger parasitic capacitance likely to load the bit line. On top of this, the internal supply line voltage (Vint) is now reduced to such a low power level that it compresses the output difference still further in read signals between memory data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d.
Supposing a conducting transistor 11 is energized by an internal supply line voltage, Vint, directly from the bit line 12 and word line 13, the source S will be at a potential level of Vintxe2x88x92VT. When read current flows from a capacitor 10, a sensing amplifier reads the level of bit line 12 at Vintxe2x88x922VT volts, with a voltage drop across transistor 11 taken into account.
The occurrence of inaccurate reading probabilities could be prevented when the word line 13 voltage is boosted. The reduction of a bit line voltage causes memory reading accuracy likely to be impaired by transistor threshold value, VT; when the bit line 12 and word line 13 are charged with Vint and Vint+VT, respectively, the transistor source S is at Vint, higher than before, to render further reading accuracy deterioration to be prevented. Here a symbol, VBOOT, should be introduced in order to refer to transistor gate voltage. The internal supply lines have means to generate raised supply voltage VBOOT, as needed, to a gate of the switching transistor; for an example, a DRAM for VCC equal to 3.3 volts, VBOOT will be equal to 5.1 volts.
Technically, DRAM output includes p-channel and n-channel MOS transistors interconnected, an example is shown in FIG. 2. P-channel MOS transistors read a power supply VCC at terminal DATA OUT, without being affected by voltage drops across a conducting transistor albeit at slow recovery time from 0 to Vint volts, due to an inherently small driving current. N-channel MOS transistors have a faster switching rate, except for the gate voltage that needs to be raised to make up for the voltage drop at the output, as observed previously. An inverter circuit in FIG. 2 achieves high speed switching by having two n-channel MOS transistors, 14 and 16, connected to an output terminal, DATA OUT, with a transistor 14 gate energized at VBOOTQ. Transistors 14 and 16 receive two complementary signals, OUT and {overscore (OUT)} at the gates, as shown. Example: VCC equal to 3.3 volts, VBOOTQ as required is 4.5 volts, which demonstrates another case of an internal supply line serving to generate a raised power level to a bit line in addition to a word line, as previously dealt with, in the switching transistor devices.
After production prior to shipment, DRAM devices go to a burn-in testing station. Burn-in tests are performed under voltage stress in order to reduce the initial failure rate of the DRAM devices. For DRAM devices of rated external power supply at 3.3 volts (VCC), a stress level of 5.2 volts in the external power supply is required to run burn-in tests, whereby the internal power supply rises to 7.5 volts, causing in turn VBOOT voltage to rise from a calculated level of about 7 volts in normal switching condition to 10 volts or more momentarily at the source and the drain of the transistor during burn-in tests. This is counteractive indeed to DRAM devices of the current rapidly growing trend of micro-miniaturization, when the supply voltage of the integrated circuits is already low enough to render the burn-in tests liable to damage the products prior to shipment.
Internal power lines, which are semiconductor arrays in a DRAM chip, consist of means of charge pumping, sensors and clock signal generators to feed switching transistors with raised levels of voltage. If the internal supply line has a point of connection to word lines and transistor outputs (or the drains) clustered around at the end of the feeder line, transistors farther away from the feeder connection are liable to cause the energizing voltage to fall short of the requisite levels. These shortcomings will become more critical with the current trend to longer DRAM bits. They will have larger internal supply lines and larger current conducting resistance causing an adversary impact upon the performance of DRAM devices in respect of readout errors and output rise time.
An object of the invention is to offer improved semiconductor memory devices that will not cause breakdown during burn-in tests in the transistors and other constituent elements at accelerating stress voltage levels on internal supply lines.
Another object of the invention is to offer improved semiconductor devices, capable of making requisite levels of voltage available, regardless of the point of connection along the internal power supply line, to the word lines and the output circuits.
A further object of the invention is to offer the driving method of such improved semiconductor devices.
One preferred embodiment of the invention refers to configuration of a semiconductor memory device including an internal supply line energized by a plurality of dispersed pumping circuits in different levels of pumping capacity, whereby they may be selectively deactivated by the burn-in mode signal to initialize performing the burn-in test.
Another preferred embodiment of the invention refers to the method of driving a semiconductor memory device including an internal supply line being energized by a plurality of dispersed pumping circuits having different levels of pumping capacity, whereby the driving method is contrived to selectively deactivate the pumping circuits by causing the burn-in mode signals to trigger the deactivation accordingly, in performing burn-in tests.
A plurality of the pumping circuits are arranged dispersively along the internal supply line so that they may be connected at least at the both ends and in the middle of the internal supply line, in the two preferred embodiments. In either embodiment, it is necessary to prioritize the deactivation of pumping circuits by size of the capacity.